1. Field of the Invention
The invention relates to a memory. Particularly, the invention relates to a memory capable of automatically adjusting write timing.
2. Description of Related Art
FIG. 1 is a schematic diagram of a memory cell of a conventional static random access memory (SRAM). FIG. 2 is a timing diagram of a word line signal, a bit line signal and a complementary bit line signal of FIG. 1. Referring to FIG. 1, when a word line signal WL of a memory cell 100 has a low voltage level (or a high voltage level; i.e. before the SRAM is operated), a bit line signal BL and a complementary bit line signal BLB are pre-charged to a high voltage level. Then, when the word line signal WL has a high voltage level (or a low voltage level; i.e. the SRAM is operated), metal oxide semiconductor (MOS) transistors M1 and M2 are turned on (i.e. a data in the SRAM has a high level when the bit line signal BL has a high voltage level and the complementary bit line signal BLB has a low voltage level or a data in the SRAM has a low level when the bit line signal BL has a low voltage level and the complementary bit line signal BLB has a high voltage level), and since the bit line signal BL and the complementary bit line signal BLB are complementary, the bit line signal BL is maintained to the high voltage level, and the complementary bit line signal BLB is pulled down from the high voltage level to the low voltage level, so as to achieve a full swing.
Since a sense amplifier in the SRAM can perform sensing when the voltage level of the complementary bit line signal BLB is pulled down by a magnitude greater than 200 mV, a mechanism of adjusting write timing is added to the SRAM, so as to achieve a power saving effect. FIG. 3 is a schematic diagram illustrating a conventional SRAM with reference bitline system to adjust write timing. Referring to FIG. 3, when the word line signal WL generated by a word line decoder 310 is transmitted to a reference bit line 320, the reference bit line 320 transmits back a cut-back signal REF_BL to cut off an excess part of the word line signal WL, so that the voltage level of the complementary bit line (not shown) in a memory cell array 320 is only pulled down by a magnitude just greater than 200 mV without being pulled down to the full swing. In this way, power consumption for again pre-charging the bit line/complementary bit line to the high voltage level is decreased, so as to achieve the power saving effect.
Due to a process shift or an uneven power line distribution of the SRAM 300, a pulling up speed of the bit line signal closed to the word line decoder 310 is relatively fast, and a pulling up speed of the bit line signal away from the word line decoder 310 is relatively slow. Therefore, a time for the reference bit line 320 generating the cut-back signal can be too short, so that the SRAM 300 may generate an error accessing operation.